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      [上海杭州]上海瀾至半導體有限公司

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      TITLE: IC Design Engineer(RTL-IP-Design)---杭州

      JOB DESCRIPTION:

      1.  Module-level architecture definition and design;

      2.  Module-level RTL implementation;

      3.  Simulation/Verification at both module level and system level;

      4.  Module-level synthesis and timing analysis;

      5.  Writing design spec and report;

      6.  FPGA/silicon debug on related modules.

      JOB QUALIFICATIONS:

      1.  Bachelor degree or Master degree in ASIC Design Relevant;

      2.  Solid knowledge on digital IC design; Strong skills of Verilog RTL coding and simulation; Hands-on experiences on EDA tools, such as Cadence and Synopsys tools; Familiar with C language;

      3.  Relevant experiences on STB products;

      4.  Good communication skills and Good oral/written English.

      TITLE System Verification Engineer---杭州/上海

      JOB DESCRIPTION:

      1.  Collect function points from design specification; generate/run/debug test cases on FPGA;

      2.  Build up and maintain FPGA test platforms;

      3.  Port ASIC to FPGA and generate bit files, including simulation, synthesis and P&R;

      4.  Help to develop driver for modules and silicon chip bring up, validation and debug.

      JOB QUALIFICATIONS:

      1.       Bachelor or Master in Electronics Engineering or related;

      2.       Familiar with AMBA, Interface, Audio/Video System;

      3.       Familiar with C, Tcl, Python;

      4.       Familiar with lab equipments, such as oscilloscope, logic analyzer, spectrum analyzer, etc;

      5.       Knowledge of PLD/FPGA design flow using Verilog/VHDL and EDA tools such as Xilinx ISE, Altera Quartus;

      6.       Experience in PCB schematic or layout is a plus;

      7.       English reading/writing, Windows office tools.

      TITLEIC Design Engineer (Synthesis/STA)---杭州

      JOB DESCRIPTION:

      1. Netlist creation and release, including environment setup, chip/IP level synthesis, linting, equivalence check, and optimization;

      2. STA regression and timing fix till closure, including environment setup, timing constraints creation, result check and status summary, timing ECO;

      3. Formal verification, including environment setup, result inspection and debug.

      JOB QUALIFICATIONS:

      1. Bachelor degree or Master degree in Electronic Engineering or Micro-electronic Science;

      2. Strong Verilog coding skills; Good understanding of SoC design flow and methodology; Hands-on experience in using at least one of the following EDA tools: Design Compiler, PrimeTime, Formality; Knowledge of sync/async design, clock/reset, type of timing violations and solutions; Familiar with UNIX environment and at least one text editing tool like VIM;

      3. Perl/Tcl scripting skill is highly preferred;

      4. Ability to read and write emails/documents/presentations in English.

      TITLE: IC Design Engineer (DFT)---杭州

      JOB DESCRIPTION

      1. Perform and/or lead various DFT tasks for the creation of SoC chips. The main areas of focus will be to architect, develop and optimize structured test solutions using DFT insertion and ATPG tools as well as BIST for memories, etc;

      2. Be responsible for architecting and integrating DFT structures into RTL and netlists to deliver reliable, efficient and high quality manufacturing test coverage.

      JOB QUALIFICATIONS:

      1. Architect DFT strategies for complex SoC designs;

      2. Generate and insert Scan, Memory BIST, Boundary Scan, Test Compression etc;

      3. Generate ATPG vectors for stuck-at, transition fault and other types;

      4. Determine, analyze and enhance fault coverage to achieve target test quality;

      5. Good knowledge of DFT, including scan, boundary scan, BIST, fault models and ATPG;

      6. Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, Python, csh;

      7. Excellent RTL and gate level debug skills;

      8.Formal analysis/STA Experience is a plus.

       

      TITLE: RF/Analog IC Design Engineer---上海

      JOB DESCRIPTION:

      RF/Analog block design for wireless application ICs.

      JOB QUALIFICATIONS:

      1.         PhD or MSEE with 1+ year’s experience in RF/Analog IC development;

      2.         Advanced skills in the following areas:

      ·           RF circuit design:

      LNA, Mixer, Power Amplifier, Power Detector, VCO, Synthesizer

      ·           Analog circuit design:

      Analog filter, PGA/VGA, Calibration, RSSI, Opamp

      ·           Power management circuit design:

      Voltage Regulator, DC-DC Converter

      Other qualifications:

      1.         Good understanding of device physics and CMOS fabrication processes;

      2.         Good understanding of layout tradeoffs for optimal performance and die area;

      3.         Proficiency with simulation tools including Spectre & SpectreRF. Verilog-AMS, Matlab and EM simulation is a plus;

      4.         Demonstrated ability for characterization of block and chip performances in lab and ATE environments;

      5.         Understanding of analog/digital signal processing & communication system theory is a plus;

      6.         Design experiences in deep-submicron (<65nm) process is a plus;

      7.         Great communication abilities, both oral and written;

      Self-motivation & team player.


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